Write a Verilog module for the FSM and demonstrate its operation using a VIVADO

Q1)
Consider a parking lot with a single entry and exit gate.

Two pairs of sensors, SF
and SB
, are used at the gate. When
a car is between the photo transmitter and the photo
receiver, the light is blocked, and the corresponding sensor
output is asserted to 1. For entrance, when both sensors are
unblocked, SB SF=”00″. As the car enters, Sensor SB is
blocked, making SB SF=”10″. When both sensors are
blocked, SB SF=”11″. As the car moves forward, first Sensor
SB is unblocked, resulting in SB SF=”01″. Then, sensor SF is
unblocked, making SB SF=”00″. For exit, the sensors are
blocked in the reverse order.
Design an FSM with two input signals, SB and SF and two
output signals, ENTER and EXIT. The ENTER and EXIT signals
are asserted one clock cycle when a car enters and exits,
respectively.
SBSFWrite a Verilog module for the FSM and demonstrate its operation using a testbench.
Optional
: ENTER and EXIT can be used to increment and decrement the parking occupancy
counter. The design should ensure that no car can enter the parking lot if
it is full, considering
its capacity of 64 cars.
RDY00
IN10
IN11
IN01
SB SF/ENTER EXIT
11/00
11/0001/00
11/0010/00
10/00 01/0000/00
OUT01
OUT11
OUT10
11/0011/0010/0001/00 10/0001/0000/10
RDY0000/01
00/00 10/00 11/0000/0001/00 11/00RDY00module parking_lot (
input CLK, RST,
input SB, SF,
output reg
ENTER, EXIT)
localparam
RDY00=3’d0,

IN10=3’d1, IN11=3’d2, IN01=3’d3,
OUT01=3’d4, OUT11=3’d5, OUT10=3’d6;
reg [2:0] present_state, next_state;
…
end
module
module counter(
input CLK,RST,
input ENTRY, EXIT,
output reg [5:0] occupancy);
always
@(
posedge
CLK)
begin
if (RST) occupancy <= 0;
else if (ENTRY) && (occupancy<64)
occupancy <= occupancy + 1;
else if (EXIT)
occupancy <= occupancy - 1;
end

COMPE 470 – Digital Circuits
Homework Assignment 6, Due: Tuesday April 30, 2024 at 11:59 PM
Department of Electrical and Computer Engineering
San Diego State University
(Q1) Consider a parking lot with a single entry and exit gate.
Two pairs of sensors, SF and SB, are used at the gate. When
a car is between the photo transmitter and the photo
receiver, the light is blocked, and the corresponding sensor
output is asserted to 1. For entrance, when both sensors are
unblocked, SB SF=”00″. As the car enters, Sensor SB is
blocked, making SB SF=”10″. When both sensors are
blocked, SB SF=”11″. As the car moves forward, first Sensor
SB is unblocked, resulting in SB SF=”01″. Then, sensor SF is
unblocked, making SB SF=”00″. For exit, the sensors are
blocked in the reverse order.
SB
SF
Design an FSM with two input signals, SB and SF and two
output signals, ENTER and EXIT. The ENTER and EXIT signals
are asserted one clock cycle when a car enters and exits,
respectively.
Write a Verilog module for the FSM and demonstrate its operation using a testbench.
Optional: ENTER and EXIT can be used to increment and decrement the parking occupancy
counter. The design should ensure that no car can enter the parking lot if it is full, considering
its capacity of 64 cars.
SB SF/ENTER EXIT
RDY00
10/00
IN10
00/00
01/00
00/00
11/00
10/00
11/00
00/00
11/00
IN11
10/00
11/00
01/00
11/00
IN01
00/10
RDY00
10/00
00/01
10/00
OUT01 11/00 OUT11
OUT10
RDY00
01/00
module parking_lot (input CLK, RST,
input SB, SF,
output reg ENTER, EXIT)
localparam RDY00=3’d0,
01/00
01/00
11/00
IN10=3’d1, IN11=3’d2, IN01=3’d3,
OUT01=3’d4, OUT11=3’d5, OUT10=3’d6;
reg [2:0] present_state, next_state;
…
endmodule
module counter(input CLK,RST,
input ENTRY, EXIT,
output reg [5:0] occupancy);
always @(posedge CLK) begin
if (RST) occupancy